Clamping circuits respectively charge a capacitor to modify the DC component of an applied signal to a reference voltage level. An input AC signal applied to the capacitor is DC offset by that charged voltage level. The capacitor may be charged by a differential amplifier which compares the charge level of the capacitor to a reference, the amplifier charging and discharging the capacitor to maintain the desired voltage. This referred to as a feedback clamp.
One application for a feedback clamp is in a digital television color receiver. In one kind of receiver the clamping capacitor receives a composite video signal which is to be clamped to a blanking signal level. The clamped video signal is then applied to an analog-to-digital converter (ADC) for digitizing the video signal. The analog-to-digital converter receives reference voltages of different values in a given range one of which values corresponds to desired level for the composite video signal blanking level. A differential amplifier compares the voltage level of the clamping capacitor charge to a reference voltage value corresponding to the ADC reference value for charging or discharging the capacitor accordingly. A clamp enable pulse is applied to the differential amplifier for causing the clamp to operate during the blanking interval so as to not interfere with the active, that is, the AC, video portion of the video signal. The resulting digitized output signal is applied to a digital signal processor which separates the synchronization, luminance and chrominance signals from the composite video signal in addition to other processing functions.
Other feedback clamping circuits are used in other portions of a color television receiver, for example, in the RGB processor, to clamp the signals to desired levels. If these signals are not referenced to a designated DC level, then the resultant color picture will be inaccurate. This is manifested most prominently when it is desired to use the color circuitry for displaying a black and white picture. Different offset values of the input color difference signals, if not clamped to a given reference level, when processed for purposes of obtaining a black and white picture, will result in the RGB processor interpreting the different DC levels of the resulting black and white video signals as manifesting color components. These color components appear as color hues on the black and white picture, are noticeable and undesirable.
A television picture comprises 525 raster scan lines forming a frame comprising a pair of successively generated fields, each field comprising 262.5 scan lines. The fields are interlaced in successive time intervals. A problem observed with such interlacing is that the successive interlacing of the adjacent fields, even though the lines are closely spaced to one another and interlaced in relatively short time periods, creates a condition referred to as interline flicker which may be observable in the picture.
A digital television receiver can correct for this problem. In a digital television receiver, the video signal comprising luminance and chrominance signals are processed and stored in memory. The system using an algorithm predicts the content of the video signals of each succeeding field based on information in the preceding field which is digitally stored in memory. The predicted field is also stored in memory. The predicted field is superimposed simultaneously with the proceeding occurring actual field to produce a frame without successively occurring fields as occurs in an analog receiver. That is, the 525 scan lines for each frame are generated in successive order as if occurring in a common field.
In order to perform this kind of processing, among other processing, the video information signal is stored in memory and then subsequently processed for a given design purpose. It is essential to clamp each of the luminance and chrominance signals to a reference level throughout the signal processing procedure.
In a second kind of digital color television receiver, a tuner IF circuit is included which provides a composite superheterodyne video signal to a synchronization (sync), luminance (luma) and chrominance (chrome) processing circuit. The sync, luma and chroma processing circuit separates the Y (luminance) and the U/V (color difference) signals and the horizontal and vertical synchronization signals from the composite video signal. The latter signals are applied to scan circuits for deriving horizontal and vertical drive signals for the cathode ray tube (the picture tube). The separated Y, U and V signals are applied through appropriate clamps to a digital processor. Separate clamps are provided to insure the digitized luma and color difference signals are at a desired blanking level prior to digital processing as compared to the first kind of receiver discussed above in which the composite signal is clamped by a common clamp prior to digital processing.
The clamps include analog-to-digital converters (ADC) for digitizing the analog video signal prior to being applied to the digital processor. The blanking portion comprises a relatively large portion of the video signal. Since the blanking portion is at a relatively DC level, it is desired to conserve digital processor memory by eliminating the digital processing of the digitized blanking portion in the second receiver type. The assumption is that the voltage level of the blanking portion is constant and, for each of the luminance and chrominance signals, has a known value. To conserve memory, the value of the blanking portion is inserted by the digital processor. For example, the processor includes a code word generator for generating a digital code word manifesting the value of the blanking level of each of the luma and color difference signals. In so doing, it is assumed that the video signal outputs of the analog-to-digital converters of each of the feedback clamping circuits will correspond to a given desired blanking level by reason of the fact that the clamps are set to provide for these levels. These levels are intended to be substantially identical to the reference levels represented by the code words provided by the digital processor. The digital processor inserts the code word corresponding to the desired blanking portion of the applied video signals during their blanking portion intervals.
In order to provide appropriate digital codes corresponding to their video signals, the analog-to-digital converters divide the voltage levels thereof to manifest a typical video range, for example, 256 levels. Assuming further that the ADCs have a 2 volt range, for example, 2.5 to 4.5 volts with a 3.5 volt mid range, then the ADCs have a sensitivity of about 7.8 millivolts per grey scale step. As a result, a 0.1 volt or even 0.01 volt error in the clamping circuit or in the ADC is significant relative to the sensitivity of the ADC.
The present inventors recognize that when the digital processor inserts a code word manifesting a blanking DC voltage level into the digitized video signal that code word represents a predetermined voltage level for example 3.5 volts. If the clamping circuits have an offset error of 0.1 volts, or possibly even 0.01 volts, the resulting video signal will also be offset by that amount. However, because the digital processor inserts an assumed blanking voltage value into the received digitized video signal, the video signal being clamped to the clamping level, will be offset by the error thereof relative to the blanking signal level introducing a distortion in the resulting signals and, therefore, colors of the picture.
One source of error is due to an offset in a typical ADC due, for example, to changes in temperature. Further, a differential amplifier employed in the analog loop of the clamping circuit may also introduce an offset error so that the resulting clamping level is not at the desired level.